{"title":"Optimistic distributed timed cosimulation based on thread simulation model","authors":"S. Yoo, Kiyoung Choi","doi":"10.1109/HSC.1998.666240","DOIUrl":null,"url":null,"abstract":"In this paper, we present thread-based optimistic distributed timed cosimulation methods which reduce the overhead of optimistic simulation. First, we present a thread simulation model to facilitate efficient distributed cosimulation. To reduce the overhead of optimistic simulation, we focus on the reduction of state saving overhead. Based on the thread simulation model, we perform thread-level state saving without saving the whole state of processor at each check-point. Especially, single checkpoint property based on the proposed thread model minimizes the number of state savings for HW threads. We give preliminary experimental results to show the efficiency of the proposed methods.","PeriodicalId":269781,"journal":{"name":"Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)","volume":"464 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"27","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HSC.1998.666240","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 27
Abstract
In this paper, we present thread-based optimistic distributed timed cosimulation methods which reduce the overhead of optimistic simulation. First, we present a thread simulation model to facilitate efficient distributed cosimulation. To reduce the overhead of optimistic simulation, we focus on the reduction of state saving overhead. Based on the thread simulation model, we perform thread-level state saving without saving the whole state of processor at each check-point. Especially, single checkpoint property based on the proposed thread model minimizes the number of state savings for HW threads. We give preliminary experimental results to show the efficiency of the proposed methods.