Tomonari Tanaka, I. Ikeno, Riku Tsuruoka, Takumi Kuchiba, Wang Liao, Y. Mitsuyama
{"title":"Development of Autonomous Driving System Using Programmable SoCs","authors":"Tomonari Tanaka, I. Ikeno, Riku Tsuruoka, Takumi Kuchiba, Wang Liao, Y. Mitsuyama","doi":"10.1109/ICFPT47387.2019.00091","DOIUrl":null,"url":null,"abstract":"We propose an autonomous driving system using programmable SoCs. Our system consists of two FPGA boards of Zybo Z7-20, three cameras, and one motor driver of H-bridge circuits with independent left and right motors. The main part of our system is divided into two blocks: driving control and object detection, which are implemented on each Zybo Z7-20. Within the development framework of programmable SoC of Zynq 7000, we adopt a HW/SW co-design to blance the design period and system performance to satisify the goals of the FPGA design competition.","PeriodicalId":241340,"journal":{"name":"2019 International Conference on Field-Programmable Technology (ICFPT)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International Conference on Field-Programmable Technology (ICFPT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICFPT47387.2019.00091","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
We propose an autonomous driving system using programmable SoCs. Our system consists of two FPGA boards of Zybo Z7-20, three cameras, and one motor driver of H-bridge circuits with independent left and right motors. The main part of our system is divided into two blocks: driving control and object detection, which are implemented on each Zybo Z7-20. Within the development framework of programmable SoC of Zynq 7000, we adopt a HW/SW co-design to blance the design period and system performance to satisify the goals of the FPGA design competition.