Enhanced fault modeling for DRAM test and analysis

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's Pub Date : 1991-04-15 DOI:10.1109/VTEST.1991.208150

H.-D. Oberle, M. Maue, P. Muhmenthaler

引用次数: 27

Abstract

For typical physical DRAM cell array defects, logical fault models are derived. These models completely and unambiguously describe all coupling faults and pattern sensitivities. Thus, test patterns are developed for production tests and fault analyses with high fault coverage.<>

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增强了对DRAM测试和分析的故障建模

针对典型的物理DRAM单元阵列缺陷，导出了逻辑故障模型。这些模型完整而明确地描述了所有耦合错误和模式敏感性。因此，为具有高故障覆盖率的生产测试和故障分析开发了测试模式

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's

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