Optimized Polynomial Multiplier Over Commutative Rings on FPGAs: A Case Study on BIKE

Abstract

In this paper, we present two constant-time FPGAbased polynomial multipliers for post-quantum secure key encapsulation mechanisms based on quasi-cyclic codes, which are among round 2 candidates in the NIST PQC standardization process. The pipelined hardware architecture for polynomial multiplications proposed in this work are fully parameterized in terms of the size of the polynomial, and can be further tuned flexibly to achieve a trade-off between time and area depending on individual needs. We also present a case study on the BIKE key generators which use these two polynomial multiplier architectures as building blocks. Compared with the state-of-the-art hardware implementation of BIKE, the design proposed in this work is around 9× faster in terms of run-time while maintaining an over 6× smaller time-area product.