Custom 12-Bit, 500MHZ ADC/Data Processing Module for the KOTO Experiment at J-Parc

Abstract

The paper presents a custom 4-Channel, 12-Bit, 500 MHz ADC/Data Processing Module, designed for the Step1 of the KOTO Experiment at J-Parc, Japan. This 6U VME Board will receive signals from the Beam Hole Photon Veto Detector, and will be one of the several different ADC Modules in the Experiment's Data Acquisition System (DAQ). In KOTO, the main ADC/DAQ system runs at a 125 MHz simultaneous sampling rate, provided by one low jitter 125 MHz system clock. The 500 MHz ADC Module receives this system clock and multiplies its frequency by four with a local Zero Delay Clock Generator. The four analog input pulses are amplified and passed to the 12-Bit, 500MHz monolithic pipeline ADC chips. After sampling, data are processed locally with a field programmable gate array (FPGA). The module is provided with a pipeline, up to 40us (20,480 samples) long, which stores the acquisitions, awaiting the system Level 1 trigger pulse. After a trigger, data are packed and buffered for readout. The readout can be performed via the VME32/64 backplane, or via the two front panel optical links. Designed specifically for the KOTO Experiment, this module can also be used in many other Physics applications. The board can receive the analog input signals in both single ended or differential modes and it can run with a local oscillator or with input clocks in the range of 32.5MHz to 550MHz. The design and preliminary test results will be described.