Systematic memory test generation for DRAM defects causing two floating nodes

Abstract

The high complexity of the faulty behavior observed in DRAMs is caused primarily by the presence of internal floating nodes in defective DRAMs. This paper describes a new analysis method to apply electrical simulation for investigating the faulty behavior resulting from defects causing two floating nodes within the memory. The paper also presents the results of a simulation study performed on bit line opens to validate the newly proposed method, and suggests a test to detect these bit line opens.