Pavan Adulapuram, C. Kumar, Tejaswini Tula, Farasha Mehroz Mohammed Abdul, Sritha Katrapally, Lavan Kumar Pakala
{"title":"A FinFET pass transistor based XOR and XNOR circuit designed for 18nm technology","authors":"Pavan Adulapuram, C. Kumar, Tejaswini Tula, Farasha Mehroz Mohammed Abdul, Sritha Katrapally, Lavan Kumar Pakala","doi":"10.1109/IConSCEPT57958.2023.10169937","DOIUrl":null,"url":null,"abstract":"Due to significant short-channel effects scaling circuits for typical single-gate MOSFET’s is extremely difficult. Circuits are scaled down to rise operational speed, consume less space, and improve control over channel by gate configurations. But as a result of diluted geometries, lower supply voltage and higher frequencies all have impact on device, scaling faces a number of challenges. The short-channel effect issue in MOSFETs is subsidized by the use of FinFET. For good control, a second gate is added to double gate device and is placed opposite to first gate. The mostly used subcircuits particularly in arithmetic circuits are EX-OR, EX-NOR circuits which are created to boost speed and power. As a result, EX-OR, EX-NOR circuit which is based on CADENCE VIRTUOSO tool at 18nm, uses a 0.7v supply voltage performs better than a complex logic circuit.","PeriodicalId":240167,"journal":{"name":"2023 International Conference on Signal Processing, Computation, Electronics, Power and Telecommunication (IConSCEPT)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 International Conference on Signal Processing, Computation, Electronics, Power and Telecommunication (IConSCEPT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IConSCEPT57958.2023.10169937","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Due to significant short-channel effects scaling circuits for typical single-gate MOSFET’s is extremely difficult. Circuits are scaled down to rise operational speed, consume less space, and improve control over channel by gate configurations. But as a result of diluted geometries, lower supply voltage and higher frequencies all have impact on device, scaling faces a number of challenges. The short-channel effect issue in MOSFETs is subsidized by the use of FinFET. For good control, a second gate is added to double gate device and is placed opposite to first gate. The mostly used subcircuits particularly in arithmetic circuits are EX-OR, EX-NOR circuits which are created to boost speed and power. As a result, EX-OR, EX-NOR circuit which is based on CADENCE VIRTUOSO tool at 18nm, uses a 0.7v supply voltage performs better than a complex logic circuit.