9.5 Gbit/s 20 channel 1∶8 DEMUX for a coherent optical receiver DSPU ASIC input interface

Abstract

This paper presents the design of an input interface to a CMOS DSPU of an optical coherent QPSK with polarization multiplex receiver. The interface consists of a 20 channel 1:8 DEMUX. Source Coupled FET logic (SCFL) and CMOS logic were used in the design. The interface converts 10 Gbit/s input data rate to 1.25 Gbit/s at the output. The interface gives an open eye diagram at the output up to 9.5 Gbit/s input data rate. The system consumes 7.9 mW/channel.Gb/s. 130 nm bulk CMOS technology was used in the design.