Memory Speed Enhancement via SI/PI Optimization in Constrained Tablet Designs

Abstract

Achieving high speed memory in small form-factor and low PCB layer count is critical for tablets designs. This paper reports several practical SI/PI design improvements such as PTH patterning suited for common memory ball-maps, etc. Simulation data showing voltage noises and eye diagrams are presented. Finally, measurement data with speeds of 3200 MT/s are provided for successful demonstration.