{"title":"Safety-Centric Design of Distributed Embedded Avionics","authors":"R. Vemuri, M. Borowczak, A. Avakian","doi":"10.1109/NAECON.2008.4806561","DOIUrl":null,"url":null,"abstract":"This paper describes a methodology for safety-centric development of distributed embedded avionics realized as sense-actuate-control (SAC) networks. The methodology has consists of two parts. First, formal methods are used in defining and deriving families of SAC node architectures. This methodology eliminates redundant verification and validation (V&V) efforts across members of the same family of architectures. Second, proof-directed run-time error-monitor generation methodology is presented. This methodology links design-time verification with run-time error checking. Robust error monitors can be derived and reused across the members of a family of architectures.","PeriodicalId":254758,"journal":{"name":"2008 IEEE National Aerospace and Electronics Conference","volume":"197 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE National Aerospace and Electronics Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NAECON.2008.4806561","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper describes a methodology for safety-centric development of distributed embedded avionics realized as sense-actuate-control (SAC) networks. The methodology has consists of two parts. First, formal methods are used in defining and deriving families of SAC node architectures. This methodology eliminates redundant verification and validation (V&V) efforts across members of the same family of architectures. Second, proof-directed run-time error-monitor generation methodology is presented. This methodology links design-time verification with run-time error checking. Robust error monitors can be derived and reused across the members of a family of architectures.