Fabrication and characterization of fine pitch TSV integration with self-aligned backside insulation layer opening

Abstract

Through silicon via (TSV) technology is moving in the direction of miniaturization and multi-functional development, and is considered to be the main way beyond Moore's Law. This paper presents a fine-pitch TSV manufacturing method with self-aligned backside insulation layer opening for three-dimensional (3D) integration. It is characterized by the use of chemical-mechanical polished (CMP) process and deep reactive ion etching (DRIE) process instead of the traditional lithographic process. Through this method, we can guarantee the integrity of the TSV sidewall insulation and eliminate the photolithography process. Low-frequency and high-frequency electrical performance test is conducted in order to characterize its electrical properties and insulation properties.