A Review on Implementation of AES Algorithm Using Parallelized Architecture on FPGA Platform

Abstract

High-security cryptography algorithms like AES require high computational capabilities to achieve information security. Therefore, it is necessary to use parallel computing architectures that exploit modern technologies to obtain the most conceivable computational power. Various methods have been introduced to achieve parallel processing. One of them is field-programmable gate arrays (FPGAs), which have good characteristics suitable for implementing parallel architectures with lower power consumption. This paper will focus on the most important FPGA boards that were used to implement the AES cryptographic algorithm. In addition, it demonstrates the general scheme of building architecture with multiple computing processing engines to get high performance and better throughput, which is reflected in the reduced cost and energy consumption of IoT devices.