A novel VHDL-based computer architecture design methodology

Abstract

There is a need for a design methodology that allows the representation and simulation of a design at various levels of abstraction and interpretation. The single path design methodology presented is a possible solution to this problem. The basic concept of the methodology is the use of one simulation language, the VHSIC hardware description language (VHDL, Version 1076) for all phases of design. The VHDL framework allows for iterative stepwise refinement of a model. A performance (uninterpreted) model can be refined to a register transfer level (RTL) description without changing modeling environments or completely rewriting the models. As an example, the performance-modeling phase of the single path design methodology is applied to the WM machine, a superscalar computer architecture.<>