A 1.3–330-MHz direct clock synthesizer for display interface using fractional multimodulus frequency divider

Abstract

A 1.3-MHz to 330-MHz video clock synthesizer consisting of a fine-resolution fractional frequency divider and a divider-merged delta-sigma modulator (DSM) is presented. The proposed architecture provides a wide frequency range of output clock, and good jitter performance with reduced design complexity. Moreover, the divider-merged DSM guarantees the cycle-accurate frequency synthesis. The proposed fractional divider can divide the clock frequency with 4-bit fractional resolution using the proposed phase-switching technique. Fabricated in a 0.13-μm CMOS technology, the synthesizer has maximum peak-to-peak period jitter of 120 ps.