Design of a Low Power Double AES Crypto-Processor SoC

Abstract

System on a Chip (SoC) is the state of the art in VLSI design and automation today due to its impressive performance matrix in terms of power, speed, area, and design time. This paper presents the design of a SoC implementing the double AES crypto processor for better security than its single core. AES has been proved the most secured symmetric cryptographic algorithm certified by USA Govt. So, its hardware implementation using SoC technology is expected to offer much better performance than that of software implementation. The chip is designed using industry-standard Verilog HDL and simulated in Altera Quartus II EDA environment. Two different symmetric keys are used to encrypt and decrypt plaintext. Moreover, mixed columns, and substitution byte functions are simplified to minimize the complexity of the proposed design. The experimental study shows that the proposed AES crypto-processor SoC outperforms the existing works in terms of power requirement.