SYSTARS: A CAD tool for the synthesis and analysis of VLSI systolic/wavefront arrays

Abstract

Research on mapping regular iterative algorithms onto dedicated systolic/wavefront arrays has been directed toward defining a unified framework in which to represent and formally synthesize and analyze systolic array designs so that the design can be supported, or even automated, by a computer-aided-design system. The author presents such a design system, SYSTARS, which supports the design trajectory from algorithm to partitioned systolic array with a very flexible, comprehensive, and animative 3-D graphics environment, and extends the partitioning of full-size arrays with a fully automatic adaptive cluster algorithm and corresponding control extraction. SYSTARS effectively uses geometric representations of the algorithm, full-size systolic array, and partitioned systolic array, which makes is appropriate for the development of better systolic algorithms, better mappings, and better partitioning strategies.<>