Sung-Woo Kwon, Han-Jun Choi, Seung-Ho Oh, Moon-Key Lee
{"title":"A Fully Programmable Systolic Pipelined Digital Video Encoder For NTSC/PAL/PALplus Compatibility On A 4:3 Screen","authors":"Sung-Woo Kwon, Han-Jun Choi, Seung-Ho Oh, Moon-Key Lee","doi":"10.1109/icce.1997.625945","DOIUrl":null,"url":null,"abstract":"A proposed encoder supports NTSC and PAL systems. I n addition, it also permits PALplus standard mode compatible to16.9 wide screen on a 4:3 screen. I n order for this to be realized, vertical and horizontal synchronous timings are fully programmable and the encoder is designed in systolic pipelined architecture with double pixel clock to increase an internal processing speed Also, we have mainly concentrated on cutting down area of the encoder as much as possible. Submodules like letter-box converter, color converter matrix, low pass jilter, interpolator, and color modulator have area saving architectures. The encoder can accept RGB and YCbCr as the input pixel signal type in the speed of 10-1SMpps. Outputs are a Y/C (S-video) signal and a composite signal .We have modeled the encoder in Yerilog-HDL and verified its operation in each mode with C-language based program.","PeriodicalId":127085,"journal":{"name":"1997 International Conference on Consumer Electronics","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 International Conference on Consumer Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/icce.1997.625945","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A proposed encoder supports NTSC and PAL systems. I n addition, it also permits PALplus standard mode compatible to16.9 wide screen on a 4:3 screen. I n order for this to be realized, vertical and horizontal synchronous timings are fully programmable and the encoder is designed in systolic pipelined architecture with double pixel clock to increase an internal processing speed Also, we have mainly concentrated on cutting down area of the encoder as much as possible. Submodules like letter-box converter, color converter matrix, low pass jilter, interpolator, and color modulator have area saving architectures. The encoder can accept RGB and YCbCr as the input pixel signal type in the speed of 10-1SMpps. Outputs are a Y/C (S-video) signal and a composite signal .We have modeled the encoder in Yerilog-HDL and verified its operation in each mode with C-language based program.