{"title":"1-D discrete time CNN with multiplexed template hardware","authors":"Gabriele Manganaro, J. P. D. Gyvez","doi":"10.1109/CNNA.1998.685384","DOIUrl":null,"url":null,"abstract":"While VLSI of CNNs has seen significant progress in two-dimensional signal processing little has been done for one-dimensional applications such as audio signal processing and 1-D filtering. The paper presents a discrete-time programmable cellular neural network suitable for these kind of applications. The proposed VLSI implementation is based on the well-known S/sup 2/I technique that among other properties minimizes clock feedthrough effects. This feature renders an accurate signal processing unit. The system's main building blocks are an analog shift register and a switched current multiplier. Yet, the system architecture is novel by itself. Namely, the number of multipliers has been minimized by sharing the multipliers between the A*y and B*u products during the various phases of the controlling clock. The paper presents detailed simulation results of the system architecture.","PeriodicalId":171485,"journal":{"name":"1998 Fifth IEEE International Workshop on Cellular Neural Networks and their Applications. Proceedings (Cat. No.98TH8359)","volume":"605 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1998 Fifth IEEE International Workshop on Cellular Neural Networks and their Applications. Proceedings (Cat. No.98TH8359)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CNNA.1998.685384","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
While VLSI of CNNs has seen significant progress in two-dimensional signal processing little has been done for one-dimensional applications such as audio signal processing and 1-D filtering. The paper presents a discrete-time programmable cellular neural network suitable for these kind of applications. The proposed VLSI implementation is based on the well-known S/sup 2/I technique that among other properties minimizes clock feedthrough effects. This feature renders an accurate signal processing unit. The system's main building blocks are an analog shift register and a switched current multiplier. Yet, the system architecture is novel by itself. Namely, the number of multipliers has been minimized by sharing the multipliers between the A*y and B*u products during the various phases of the controlling clock. The paper presents detailed simulation results of the system architecture.