Less Reliable Page Error Reduction for 3D-TLC NAND Flash Memories with Data Overhead Reduction by 40% and Data-retention Time Increase by 5.0x

Abstract

This paper proposes Less Reliable Page Error Reduction (LRPER) to achieve both high reliability and small data overhead of 3D-TLC NAND flash memories. LRPER suppresses both lateral charge migration and vertical charge de-trap without redundant reading of memory cells, thus achieving fast write. In addition, data overhead is small by adding flag bits to the highly reliable page. As a result, the data-retention lifetime increases by 5.0-times. The proposal can be implemented in the SSD controller for highly reliable 3D-NAND flash.