An electrical technique for determining MOSFET gate length reduction due to process micro-loading effects in advanced CMOS technology

Abstract

A test structure was designed to enable an electrical determination of gate length reduction due to micro-loading effects in poly. A transistor with parallel dummy poly's and transistors with isolated poly's were compared. We propose that DIBL effects be used to extract gate length reduction without being affected by any parasitic resistance in source/drain regions. The results agreed well with cross-section SEM analysis, and were confirmed by the measured and simulated speeds of NAND/NOR ring oscillator circuits.