{"title":"Design of a 2.4-GHz differential low noise amplifier using 180nm technology","authors":"Nandini Shrivastava, R. Khatri","doi":"10.1109/RISE.2017.8378206","DOIUrl":null,"url":null,"abstract":"A differential input differential output low noise amplifier is proposed here. The designing is done using UMC 180nm CMOS RF process. The low noise amplifier (LNA) circuit operates at 2.4-GHz frequency. This paper presents the LNA with inductive degenerated topology using cascoded CMOS architecture in order to provide the improved gain, linearity and better isolation. It provides a better stability. The simulation and analysis is performed using Cadence Virtuoso IC tool. This design exhibits a gain of 12.68 dB, input return loss (S11) of −13.5 dB, reverse isolation (S12) of −33.85 dB and S22 equals to −10 dB. It produces a Noise Figure of 3.14 dB. The circuit operates at supply voltage of 1.8V.","PeriodicalId":166244,"journal":{"name":"2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RISE.2017.8378206","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
A differential input differential output low noise amplifier is proposed here. The designing is done using UMC 180nm CMOS RF process. The low noise amplifier (LNA) circuit operates at 2.4-GHz frequency. This paper presents the LNA with inductive degenerated topology using cascoded CMOS architecture in order to provide the improved gain, linearity and better isolation. It provides a better stability. The simulation and analysis is performed using Cadence Virtuoso IC tool. This design exhibits a gain of 12.68 dB, input return loss (S11) of −13.5 dB, reverse isolation (S12) of −33.85 dB and S22 equals to −10 dB. It produces a Noise Figure of 3.14 dB. The circuit operates at supply voltage of 1.8V.