Speed and area analysis of memory based FFT processors in a FPGA

Abstract

In this paper we present a trade-off analysis between hardware size and speed performance, measured in clock cycles, concerning fixed-point, memory-based FFT processors designed for FPGA. For OFDM systems using fixed-point FFT processors we also provide bit width requirements for different FFT sizes and digital modulation schemes including QPSK, 16-QAM, 64-QAM, 256-QAM. The information provided is based on six individual FFT processors which were modeled in software using the Java programming language, designed in HDL using Verilog and implemented in hardware using the Xilinx Spartan-3 FPGA.