Analysis of on-chip digital noise coupling path for wireless communication IC test chip

2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo) Pub Date : 2015-11-01 DOI:10.1109/EMCCOMPO.2015.7358360

Satoshi Tanaka, Peng Fan, Jingyan Ma, H. Aoki, M. Yamaguchi, M. Nagata, S. Muroga

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引用次数: 2

Abstract

In-band spurious tones of a LTE-class radio frequency integrated circuit (RFIC) receiver test element group (TEG) chip was studied in order to evaluate the degree of noise suppression by means of soft magnetic thin film. A 2-μm-thick crossed anisotropy multilayered Co-Zr-Nb film was applied onto the passivation layer of TEG chip. The in-band spurious was suppressed by 10 dB while it had no influence upon wanted signal. A magnetic near field map measured in the 2.1 GHz range indicated several noise coupling paths on chip, which were compared with the chip layout design to estimate victim wires. EM simulation model in connection with circuit simulation is carefully constructed. RF control wirings were most responsible wires than other wires and air couplings. EM simulation predicted the magnetic film should suppress noise by the maximum of 33 dB while it was 10 dB experimentally because of Si substrate coupling and board coupling.

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无线通信集成电路测试芯片片上数字噪声耦合路径分析

研究了lte级射频集成电路(RFIC)接收机测试元件组(TEG)芯片的带内杂音，以评价软磁薄膜对噪声的抑制程度。在TEG芯片的钝化层上涂覆了一层2 μm厚的交叉各向异性多层Co-Zr-Nb薄膜。带内杂散被抑制了10 dB，对想要的信号没有影响。在2.1 GHz范围内测量的磁场图显示了芯片上的几种噪声耦合路径，并将其与芯片布局设计进行了比较，以估计受害线。建立了结合电路仿真的电磁仿真模型。射频控制线是最负责任的电线比其他电线和空气耦合。电磁仿真结果表明，由于硅衬底耦合和电路板耦合的影响，该磁膜对噪声的抑制最大可达33 dB，而实验结果仅为10 dB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)

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