Low leakage and minimum energy consumption in CMOS logic circuits

Abstract

This paper presents a novel design to reduce sub threshold leakage current. The leakage controlled transistors are utilized to change dynamically the ground voltage level which is based on output voltage level of logic gate. The leakage controlled transistors (LCT's) are utilized to reduce the leakage power and static energy consumption (static power-delay product) while maintaining the performance of delay. Simulation result based on 32nm Berkeley predictive technology model shows that the proposed technique achieves better performance than conventional designs.