FPGA Implementation of Novel Lossless ECG Compression Algorithm for Low Power Devices

Abstract

A method for the lossless reduction of interface electrocardiograms (ECG) has been devised for the massive implementation of integrated circuits. The Novel approach to prediction and focuses on achieving high performance while maintaining a minimal level of complexity. This resulted in circumstances that made accurate forecasting possible through a method that solved the optimal conditions. This system provides a Very Large Scale Integration (VLSI) system that uses an effective lossless data compression technique to reduce the loss transmission rate and reduce memory size while encoding ECG data. Technology is defined as being lossless. This ability has been taken advantage of by creating a memory-less architecture that operates at a high clock rate in VLSI. The proposed compression technique aims to increase high accuracy, reduce power consumption, and reduce transfer time. Effective conditional prediction model and adaptation information for the Modified Golomb Rice Framework (MGRF) are the proposed ECG lossless compression. The proposed lossless compression has been implemented in Xilinx ISE 13.1 and Spartan 7 FPGA devices using Verilog RTL code, and it achieves the highest possible level of performance, reduces the gate size, and low power consumption.