A Case Study of Complementary-multiply-with-carry Method on OpenCL FPGA

Abstract

Field-programmable gate arrays (FPGAs) are becoming a promising heterogeneous computing component for scientific computing. The emerging high-level synthesis tools provide a streamlined design flow to facilitate the use of FPGAs for researchers who have little FPGA development experience. In this paper, we present our implementations of a pseudorandom number generator in a high-level programming language OpenCL, and evaluate its performance and performance per watt on an Arria10-based FPGA platform. We describe the complementary-multiply-with-carry method, and explore its OpenCL implementations under the constraint of hardware resources on the target device. The experimental results show that the raw performance of the implementations on an Intel Arria 10 GX1150 FPGA is 15X lower than that on an Intel Xeon 16-core CPU, but the dynamic power consumption on the FPGA is 60X lower than that on the CPU. For large data size, the performance per watt on the FPGA is 6.7X higher than that on the CPU.