VHDL signal analysis in VALET

Abstract

Design methodologies based on the reuse of existing components are needed to satisfy IC design productivity requirements. In this paper, we present our progress in developing the VHDL Assistant Low Efforts Tool (VALET) which is under development in the Department of Computer Science at the University of Victoria, Canada. VALET aims to automatically extract information from VHDL code with the goal of assisting designers in reusing components. Our motivation is that quite often the available VHDL descriptions have been developed by others, are incomplete or partially documented, and/or are too complex to promote reuse without some level of automated analysis.