Single-Bit Architecture Cache Memory Design Analysis

Abhishek Srivastava, Shashank Saxena, Tarun Sikarwar
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Abstract

This work includes the design of voltage and current difference latches and low-power cache memory for a single-bit processor core architecture. To save power, the single-bit cache memory uses voltage differential sensing amplifiers.
单位结构缓存存储器设计分析
这项工作包括设计电压和电流差锁存器和低功耗缓存的一个单比特处理器核心架构。为了节省功耗,单比特缓存存储器采用电压差分传感放大器。
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