Hardware Accelerators for Edge Enabled Machine Learning

Abstract

The proliferation of IoT devices in recent years has resulted in an exponential increase in data being transmitted over the internet. The traffic is slated for further increase in the coming years and will result in excessive network congestion and high latency. To alleviate this problem, an alternate approach needs to be considered. A prominent option would be to move the computing domain to the edge device. This option is constrained due to reduced computing, storage and power available on the edge. A novel approach combining both software and hardware solutions is required to perform analytics at the edge. This paper proposes an architecture for analysing data on the edge, combining hardware and software solutions. The proposed methodology explores machine learning algorithms for edge computing combined with the use of hardware accelerators to achieve truly intelligent edge devices. A qualitative and quantitative comparison of performance of various algorithms on CPU, GPU, FPGA platforms is carried out. A machine learning model for predicting Remaining Useful Life (RUL) for a multivariate time series dataset is developed and its deployment on the edge is discussed. The results of the experiments carried out are promising and hold potential for further research.