On Die SSN Methodology for High Speed IO

Abstract

In this paper, we discuss the methodology of on-die simultaneous switching noise (SSN) simulation in high speed parallel bus like DDR5 associated with on-die capacitance and package inductance. The on-die supply ripple is typically larger than PCB power distribution network (PDN) noise even with a very good PCB PDN design. Resonance due to package inductance and on-die capacitance creates an impedance peak in the frequency domain and undesirable voltage noise in the time domain.