Realization of Logic Operations Through Optimized Ballistic Deflection Transistors

Abstract

In this paper, the utilization of recently proposed ballistic deflection transistors (BDT) is investigated for the realization of the complete family of logic functions. BDT performance is optimized through its structural modification which is followed by the Monte Carlo simulations for 2- input logic gate functionalities at room temperature. BDT is a quasi-ballistic planar device based on InGaAs/InAlAs/InP heterolayer. The faster non-scattering transport obtained in the two dimensional electron gas (2DEG) layer facilitates smaller transit time and high performance needed for high speed circuitry.