On the design of path delay fault testable combinational circuits

Abstract

A theoretical framework for investigating the design for the path-delay-fault testability problem is provided. Necessary and sufficient conditions for the existence of general robust tests in a multioutput, multilevel circuit are given. The conditions for the existence of a more restricted class of robust tests are derived from those for general robust tests. A design procedure is given for the synthesis of multioutput, multilevel combinational logic circuits in which all path delay faults are robustly detectable. A powerful factorization method, that of extended factorization, was exploited for this purpose.<>