Exploration of Autonomous Error-Tolerant (AET) Celluar Networks in System-on-a Package (SoP) for Future Nanoscle Electronic Systems

Abstract

In this paper, we propose a nanocore/CMOS hybrid system-on-package (SoP) architecture that is suitable for any emerging nanotechnology. It combines the high density of nanoscale devices and some excellent properties of current CMOS technology including high voltage gain and interconnection bandwidth and speed. The local computing cell is autonomous and error-tolerant (AET cell), interconnected with nearest neighbors through crossbar interconnect arrangement. Some key issues are studied in more detail: a possible communication network adopting time-division-multiplexing scheme; power distribution network; sensor and control network