Low Power DET Flip-Flops Using C-Element

Abstract

To achieve compact space, high speed and low power in VLSI design is currently the core goal of research personnel. Due to its excellent performance and low power usage, dual edge triggered (DET) approach is the most preferred choice among researchers in the field of VLSI designing. At 50% of clock frequency, DET approaches deliver the same throughput as single edge triggered (SET) systems. The DETFF that is suggested with combination of 2p-1n structure and the C-element circuit. The proposed circuit multiplexes two input latches to one output in a Latch-MUX DET flip-flop by operating in both positive and negative clock cycles. The other structure balances out any errors or glitches that occur in one of the structures. This layout generates output that is fully error-free and can raise system performance. The latches is level-triggered by opposing clock levels to guarantee that every change at the input is always followed by a latch.