Role of Stress/Strain Mapping in Advanced CMOS Process Technology Nodes

Abstract

Multiple-gate MOSFETs have emerged as potential candidates for the future device generations considering the continuous increase in performance requirements. Therefore, a great demand to control strain/stress and their variation in MOSFETs has recently emerged. In this work, biaxial and uniaxial strain techniques are implemented in the device channel for both p- and n-type MOSFETs. Stress/strain mapping in strained-Si and SiGe channel trapezoidal tri-gate FinFET devices are studied through three-dimensional (3D) numerical simulation, with particular focus on enhancement of drain current. Following the strain/stress profiles simulated, the piezoresistive changes are implemented in the simulator to describe the strain effects on device operation.