An enhanced ECA/Chaotic-based PRNG: Hardware design and Implementation

Abstract

This contribution is a hardware design and implementation of an enhanced Pseudo-Random Number Generator (PRNG) dedicated to security applications on a Field Programmable Gate Array (FPGA). This high-performance Lorenz chaotic-based PRNG is improved using Elementary Cellular Automata for key encoding. Then, the hardware design of the PRNG is developed with the Xilinx System Generator software tools. The implementation is targeted at an FPGA Zedboard operating at a high throughput of 49946.62 Mbps and a good operating frequency of 195.104 MHz. The NIST 800–22 SP test suite results validate the efficiency of this hardware PRNG in high-quality random numbers generation. Furthermore, an application of this enhanced hardware PRNG in an image encryption/decryption application is offered. Compared to some recent works, the experimental results indicate that this work offers better resource utilization, throughput, and power consumption results.