A wideband unity-gain buffer in 0.13-μm CMOS

Kamyar Keikhosravy, Pouya Kamalinejad, S. Mirabbasi, Victor C. M. Leung
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引用次数: 8

Abstract

In this paper, an ultra wideband analog voltage-mode buffer is presented which can drive a load impedance of 50 Ω. The presented feedback-based buffer uses a compound amplifier which is a parallel combination of a high-DC gain operational amplifier and a operation transconductance amplifier to achieve a high unity gain bandwidth. A proof-of-concept prototype is designed and fabricated in a 0.13 μm CMOS process. The simulation and measurement results of the proposed buffer are in good agreement. The prototype buffer circuit consumes 7.34 mW from a 1.3-V supply, while buffering a 2 GHz sinusoidal input signal with a 0.4 V peak-to-peak (Vpp) amplitude and driving an AC-coupled 50-Ω load.
一种0.13 μm CMOS宽带单位增益缓冲器
本文设计了一种可驱动负载阻抗为50 Ω的超宽带模拟电压型缓冲器。所提出的基于反馈的缓冲器采用高直流增益运算放大器和跨导运算放大器并联组合的复合放大器来实现高单位增益带宽。在0.13 μm CMOS工艺中设计并制造了概念验证原型。仿真结果与实测结果吻合较好。原型缓冲电路从1.3 V电源消耗7.34 mW,同时缓冲2 GHz的正弦输入信号,峰值(Vpp)幅度为0.4 V,并驱动交流耦合50-Ω负载。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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