Efficient Metal Inter-Layer Via Utilization Strategies for Three-dimensional Integrated Circuits

Abstract

Three-dimensional integrated circuit (3D-IC) technology gained prominence for future integrated chips (ICs) due to increased transistor density at the same technology node. Conventional 3D-IC implementation involves die stacking with vertical interconnects realized by through-silicon-via (TSV). One of the main challenges associated with 3D-IC technology is the TSV size since they are large in size (100-400x larger than standard cells in 45nm technology) and their diameters do not scale with technology. In addition, lot of dummy TSVs are inserted to satisfy minimum density rule laid by foundries which further increases the overhead. Also, a need for small form factor implementation of on-chip devices especially inductors are required for heterogeneous integration. In this paper, we discuss about utilizing TSVs to form on-chip inductors for various applications. On the other hand, monolithic Three-dimensional integrated circuit (M3D-IC) technology is enabled by sequential integration of substrate layers and the devices at different layers are connected by metal inter-layer via (MIV) where MIV passes through the silicon but the size very small compared with the TSV in 3D-ICs. The effective area occupied by MIV on the substrate will increase with the number of MIVs. Therefore, in this paper, we will discuss efficient strategies to reduce silicon footprint overhead by MIV through reconfiguration of silicon around MIV to design MIV-capacitor and MIV-transistor devices. TCAD simulations of 14nm channel length demonstrate that the proposed approach will reduce the silicon area of inverter by about 24% compared with the conventional approach for transistor-level M3D-IC technology.