Electrical modeling and measuring inductance in the Micro Lead Chip Carrier

Abstract

The Micro Lead Chip Carrier is a fine pitch package with low electrical parasitics due to its small size and consequently short conductive paths. This makes the package ideal for such RF applications as personal wireless communications. Several lead count packages were modeled using a rapid solution computer program developed at Rutgers University as well as a commercially available 3D solver program. Finally the same packages were measured using a Vector Network Analyzer. The results of the two sets of simulations and the measurements are compared and will be presented.