VLSI-Oriented Architecture for Two's Complement Serial-Parallel Multiplication without Speed Penalty

Abstract

A serial-parallel multiplier computes a product by multiplying a parallel input and a serial (or online) input. Serial-parallel multipliers are frequently used in digital communication systems, digital signal processing, on-line computing applications, and embedded computing and communication systems. In this paper, a VLSI-oriented, size-efficient two's complement serial-parallel multiplication architecture is proposed. In addition to its smaller size, it is also suitable for VLSI implementation because it consists of modularized logic cells and locally interconnected signals. According to the analysis results for 2- to 32- bit multiplication, the proposed architecture requires up to 30 percent smaller size without speed penalty compared to the previous architecture.