Design and implementation of CMOS rail-to-rail operational amplifiers

Abstract

The paper presents the design and implementation of six operational amplifiers with rail-to-rail input and output capability. The study characterizes several rail-to-rail input and output stages and the dependence of the op-amp's operation on different design parameters to formulate a standard design methodology that can serve as a guide for future researches and projects in the area of rail-to-rail amplifiers. The report shows the effects of the rail-to-rail stages on the op-amp's input common-mode range and output voltage swing range. The op-amps are implemented in 0.25 mum CMOS process and the simulation results achieve specifications such as gain, bandwidth, offset voltages and common-mode rejection ratio comparable with commercially available circuits.