A 65-nm CMOS P-well/Deep N-well avalanche photodetector for integrated 850-nm optical

Quan Pan, Zhengxiong Hou, Yipeng Wang, C. Yue
{"title":"A 65-nm CMOS P-well/Deep N-well avalanche photodetector for integrated 850-nm optical","authors":"Quan Pan, Zhengxiong Hou, Yipeng Wang, C. Yue","doi":"10.1109/ASICON.2013.6811921","DOIUrl":null,"url":null,"abstract":"A silicon avalanche P-well/Deep N-well photodetectors is fabricated in standard 65-nm CMOS technology without any process modification. By adopting the lightly doped P-well as the P-terminal, a wider depletion region is achieved in a deeper position from the silicon surface. This photodetector achieves a -3-dB bandwidth of 1.1 GHz and a responsivity of 160 mA/W at 12.3 V with 850 nm light input. An integrated receiver using the proposed APD is able to operate at 4 Gbps.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"178 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE 10th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON.2013.6811921","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

Abstract

A silicon avalanche P-well/Deep N-well photodetectors is fabricated in standard 65-nm CMOS technology without any process modification. By adopting the lightly doped P-well as the P-terminal, a wider depletion region is achieved in a deeper position from the silicon surface. This photodetector achieves a -3-dB bandwidth of 1.1 GHz and a responsivity of 160 mA/W at 12.3 V with 850 nm light input. An integrated receiver using the proposed APD is able to operate at 4 Gbps.
一种集成850纳米光学器件的65纳米CMOS p阱/深n阱雪崩光电探测器
采用标准65纳米CMOS技术制备了硅雪崩p阱/深n阱光电探测器,无需任何工艺修改。采用轻掺杂p阱作为p端,可在离硅表面较深的位置获得较宽的耗尽区。该光电探测器在12.3 V、850 nm光输入下的-3 db带宽为1.1 GHz,响应率为160 mA/W。使用拟议APD的集成接收器能够以4gbps的速度运行。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信