{"title":"A 65-nm CMOS P-well/Deep N-well avalanche photodetector for integrated 850-nm optical","authors":"Quan Pan, Zhengxiong Hou, Yipeng Wang, C. Yue","doi":"10.1109/ASICON.2013.6811921","DOIUrl":null,"url":null,"abstract":"A silicon avalanche P-well/Deep N-well photodetectors is fabricated in standard 65-nm CMOS technology without any process modification. By adopting the lightly doped P-well as the P-terminal, a wider depletion region is achieved in a deeper position from the silicon surface. This photodetector achieves a -3-dB bandwidth of 1.1 GHz and a responsivity of 160 mA/W at 12.3 V with 850 nm light input. An integrated receiver using the proposed APD is able to operate at 4 Gbps.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"178 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE 10th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON.2013.6811921","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A silicon avalanche P-well/Deep N-well photodetectors is fabricated in standard 65-nm CMOS technology without any process modification. By adopting the lightly doped P-well as the P-terminal, a wider depletion region is achieved in a deeper position from the silicon surface. This photodetector achieves a -3-dB bandwidth of 1.1 GHz and a responsivity of 160 mA/W at 12.3 V with 850 nm light input. An integrated receiver using the proposed APD is able to operate at 4 Gbps.