{"title":"An improved Montgomery inversion algorithm over GF(2m) targeted for low area scalable inverter on FPGA","authors":"Mohamed N. Hassan, M. Benaissa","doi":"10.1109/APCCAS.2008.4746319","DOIUrl":null,"url":null,"abstract":"Implementing public key cryptosystems like elliptic curve cryptography on lightweight devices represents an ongoing challenge. An improved algorithm for Montgomery modular inversion over GF(2m) suitable for low resource scalable implementations is proposed. Two implementations for the proposed algorithm are presented and compared. The first is based on the Xilinx PicoBlaze soft core and the second is a dedicated novel FPGA hardware architecture for the proposed algorithm which is scalable for the binary fields recommended by the NIST (up to m les 571 ) and is parameterized to support different word lengths. Both designs are fully mapped onto the smallest size and lowest cost chip from Xilinx Spartan-III family (XC3S50).","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"409 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.2008.4746319","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Implementing public key cryptosystems like elliptic curve cryptography on lightweight devices represents an ongoing challenge. An improved algorithm for Montgomery modular inversion over GF(2m) suitable for low resource scalable implementations is proposed. Two implementations for the proposed algorithm are presented and compared. The first is based on the Xilinx PicoBlaze soft core and the second is a dedicated novel FPGA hardware architecture for the proposed algorithm which is scalable for the binary fields recommended by the NIST (up to m les 571 ) and is parameterized to support different word lengths. Both designs are fully mapped onto the smallest size and lowest cost chip from Xilinx Spartan-III family (XC3S50).