J. Hora, Aileen Chris Arellano, Xi Zhu, E. Dutkiewicz
{"title":"Design of Buck Converter with Dead-time Control and Automatic Power-Down System for WSN Application","authors":"J. Hora, Aileen Chris Arellano, Xi Zhu, E. Dutkiewicz","doi":"10.1109/WPTC45513.2019.9055685","DOIUrl":null,"url":null,"abstract":"A buck converter design with an automatic power-down technique and dead-time control system intended for low power application such as a wireless sensor network is proposed. With an input voltage range of 1V to 1.2V, the buck converter regulated the output voltage at 0.8V. This buck converter operates in a pulse-width modulation technique at load current range of 1mA-100mA. The output voltage ripple measured is 7.5 m V with the peak efficiency is 94.98 %. The quiescent current $(\\mathrm{I}_{\\mathrm{q}})$ of this proposed design is about $5\\mu \\mathrm{A}$. The line and load regulation is 0.195 mV/V and 0.61mV/mA, respectively. The circuit core layout dimension is $179 \\mu\\mathrm{m}$ and $120\\mu \\mathrm{m}$ 65nm CMOS technology.","PeriodicalId":148719,"journal":{"name":"2019 IEEE Wireless Power Transfer Conference (WPTC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE Wireless Power Transfer Conference (WPTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WPTC45513.2019.9055685","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A buck converter design with an automatic power-down technique and dead-time control system intended for low power application such as a wireless sensor network is proposed. With an input voltage range of 1V to 1.2V, the buck converter regulated the output voltage at 0.8V. This buck converter operates in a pulse-width modulation technique at load current range of 1mA-100mA. The output voltage ripple measured is 7.5 m V with the peak efficiency is 94.98 %. The quiescent current $(\mathrm{I}_{\mathrm{q}})$ of this proposed design is about $5\mu \mathrm{A}$. The line and load regulation is 0.195 mV/V and 0.61mV/mA, respectively. The circuit core layout dimension is $179 \mu\mathrm{m}$ and $120\mu \mathrm{m}$ 65nm CMOS technology.