TTL Hardware Interface: A High-Level Interface for Streaming Multiprocessor Architectures

Abstract

Digital chips for multimedia applications use function-specific hardware co-processors to achieve high performance at low power consumption. These co-processors are typically equipped with traditional address-based interfaces. Networks-on-chips (NoCs) are emerging as scalable interconnect for advanced digital chips. Integration of co-processors with NoCs requires load/store packetizing wrappers on the network interfaces. This leads to unnecessary address generation and address transportation over the NoC for streaming data. By using high-level message passing interfaces for the streaming data, the co-processors can be made simpler and better reusable and the NoCs are used more efficiently. We present the task transaction level (TTL) high-level hardware interface for streaming co-processors as a concrete proposal for such an interface. We present three case study implementations and conclude that a TTL high-level message passing interface is beneficial compared to an address-based interface because it offers a better match with NoCs and it allows for better reuse and simpler design of co-processors