Environmental based characterization of soc for stratified testing

Abstract

A B Thispaperproposes II noref environmat&bmed mefhod for evaluating thegoodyield m e (CYR) of Systems-on-Chip (SoC) during fabrication Testing nndyield evoluotion at high confidence are MM of the most critical irsues for the fechnologifal SUECCSS of Soc. Since 4 SoC is designed and assembled using deeply embedded InteUecfuol Propem (IP) cores om SoC a rapidly expanding market with great potential