Test Vector Generation and Sensitivity Analysis for Hardware Trojan Detection in Compact Rare Nodes

Abstract

Hardware Trojans (HT) emerged as a significant threat to Integrated Circuits (IC) industry that require security and trustworthiness in systems. Detecting HT has become very challenging due to the diversity of Trojans and unpredictable process variations during fabrication. This work presents a test vector generation approach to improve the trojan detection process. The proposed approach tries to trigger the compact rare nodes. The nodes of digital circuit are compact, in which the transition probability is less and has high controllability and observability values are considered as compact. Since, these nodes are the potential point for Hardware Trojan insertion for attackers. Thus, our objective is to trigger those compact rare nodes and change the critical path with compact test patterns to make it very efficient in uncovering the malicious trojan added by attackers utilizing one of the side channel parameters - delay. The experimental results of the proposed method are analyzed using ISCAS’85 benchmark circuits and it shows that trojan detection can be achieved with reduced number of nodes and test vectors.