Timing margin examination using laser probing technique

Abstract

A laser probing procedure has been developed to examine the timing margin of signal paths in complex CMOS devices. In the procedure, injected current at one of the logic gate's transistor drains increases the propagation delay of the logic gate. This occurs because increased current at the transistor drain decreases the rate of charge transfer between the logic gate and its output load. By use of an indirect measurement scheme, a curve depicting laser-induced propagation delay as a function of illumination is experimentally generated. This curve is then analyzed to determine whether or not the examined signal path has critical timing.<>