{"title":"Hybrid EMODL Ling addition","authors":"J. Grad, J. Stine","doi":"10.1109/ACSSC.2002.1197052","DOIUrl":null,"url":null,"abstract":"Carry-lookahead adders have traditionally demonstrated that they are among the fastest adders available. By computing carry signals in parallel as much as possible the propagation delay of this type of adder is significantly reduced as opposed to carry propagation adders. Further algorithmic advancements have been proposed by Ling to use pseudo-carries, which are even faster to compute. For CMOS dynamic logic the EMODL adder has demonstrated that a 32-bit adder can be constructed with only 3 stages of logic and an unprecedented small hardware complexity. This paper presents a novel hybrid adder. By introducing Ling's algorithm into the EMODL adder, the critical path can be shortened with only a slight increase in hardware complexity.","PeriodicalId":284950,"journal":{"name":"Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002.","volume":"606 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ACSSC.2002.1197052","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Carry-lookahead adders have traditionally demonstrated that they are among the fastest adders available. By computing carry signals in parallel as much as possible the propagation delay of this type of adder is significantly reduced as opposed to carry propagation adders. Further algorithmic advancements have been proposed by Ling to use pseudo-carries, which are even faster to compute. For CMOS dynamic logic the EMODL adder has demonstrated that a 32-bit adder can be constructed with only 3 stages of logic and an unprecedented small hardware complexity. This paper presents a novel hybrid adder. By introducing Ling's algorithm into the EMODL adder, the critical path can be shortened with only a slight increase in hardware complexity.