Two-stage interleaving network analysis to design area- and energy-efficient 3GPP-compliant receiver architectures

Abstract

Interleaving is a key component of many digital communication systems where the encoded data is reshuffled prior to transmission to protect against burst errors. Coupled with multiplexing schemes such multi-stage subsystems achieve the necessary quality and flexibility to support a variety of different services. In 3GPP, a 2-stage multiplexing channel interleaver network is adopted. Its state-of-the-art implementation is both memory- and control-intensive, since the deinterleaving is done explicitly implying dedicated storage and processing units at each stage. In this paper, we show that the C-fold decimation property which characterizes typical block interleavers is preserved in 2-stage interleaving networks. Thus, the underlying architecture not only results in significant memory size and access rate reductions but also greatly simplifies control processing. A decline in memory size of up to 31% and in access energy of up to 54% has been observed for STMicroelectronics' 0.13 /spl mu/m CMOS technology for various 3GPP capability classes.